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data sheet 2:4, lvds output fanout buffer, 2.5v IDT8SLVD1204I IDT8SLVD1204I revision a 07/10/14 1 ?2014 integrated device technology, inc. general description the IDT8SLVD1204I is a high-performance differential lvds fanout buffer. the device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. the IDT8SLVD1204I is characterized to operate from a 2.5v power supply. guaranteed output-to- output and part-to-part skew characteristics make the IDT8SLVD1204I ideal for those clock distribution applications demandin g well-defined performance and repeatability. two selectable differential inputs and four low skew outputs are available. the integrat ed bias voltage reference enables easy interfacing of single-ended signals to the device inputs. the device is optimized for low power consumption and low additive phase noise. features ? four low skew, low additive jitter lvds output pairs ? two selectable differential clock input pairs ? differential pclk, npclk pairs can accept the following differential input levels: lvds, lvpecl ? maximum input clock frequency: 2ghz ? lvcmos/lvttl interface levels for the control input select pin ? output skew: 20ps (maximum) ? propagation delay: 300ps (maximum) ? low additive phase jitter, rms; f ref = 156.25mhz, v pp = 1v, 10khz - 20mhz: 95fs (maximum) ? full 2.5v supply voltage ? lead-free (rohs 6), 16-lead vfqfn packaging ? -40c to 85c ambient operating temperature q0 nq0 q1 nq1 q2 nq2 q3 nq3 pclk1 npclk1 vdd pullup/pulldown pulldown sel pullup/pulldown 0 1 pclk0 npclk0 vdd gnd pullup/pulldown pulldown vdd gnd reference voltage generator v ref gnd gnd gnd 1 2 3 4 12 11 10 9 1 3 14 15 16 8 7 6 5 q2 nq2 q 3 nq 3 v ref npclk0 pclk0 v dd gnd s el pclk1 npclk1 q1 nq0 q0 nq1 pin assignment IDT8SLVD1204I 16 lead vfqfn 3.0mm x 3.0mm x 0.9mm package body 1.7mm x 1.7mm epad nl package top view block diagram
IDT8SLVD1204I data sheet 2:4, lvds output fanout buffer, 2.5v 2 revision a 07/10/14 pin description and pin characteristic tables table 1. pin descriptions note: pulldown and pullup refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function table table 3. sel input selection function table note: sel is an asynchronous control. number name type description 1gndpower power supply ground. 2 sel input pullup/ pulldown reference select control pin. see table 3 for function. lvcmos/lvttl interface levels. 3 pclk1 input pulldown non-inverting differential clock/data input. 4 npclk1 input pullup/ pulldown inverting differential clock/data input. v dd /2 default when left floating. 5v dd power power supply pin. 6 pclk0 input pulldown non-inverting differential clock/data input. 7 npclk0 input pullup/ pulldown inverting differential clock/data input. v dd /2 default when left floating. 8v ref output bias voltage reference for the pclk, npclk inputs. 9, 10 q0, nq0 output differential output pair 0. lvds interface levels. 11, 12 q1, nq1 output differential output pair 1. lvds interface levels. 13, 14 q2, nq2 output differential output pair 2. lvds interface levels. 15, 16 q3, nq3 output differential output pair 3. lvds interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2 pf r pulldown input pulldown resistor 51 k ? r pullup input pullup resistor 51 k ? input operation sel 0 pclk0, npclk0 is the selected differential clock input. 1 pclk1, npclk1 is the selected differential clock input. open (default) input buffers are di sabled and outputs are static.
IDT8SLVD1204I data sheet revision a 07/10/14 3 2:4, lvds output fanout buffer, 2.5v absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or an y conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating condit ions for extended periods may affect product reliability. note 1: according to jedec/jesd js-001-2012/22-c101e. electrical characteristics table 4a. power supply characteristics, v dd = 2.5v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma 15ma v ref current sink/source, i ref 2ma maximum junction temperature, t j,max 125c storage temperature, t stg -65 ? c to 150 ? c esd - human body model, note 1 2000v esd - charged device model, note 1 1500v symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 2.375 2.5 2.625 v i dd power supply current sel = 0 or 1; f ref = 100mhz; q0 to q3 terminated 100 ? between nqx, qx 84 100 ma sel = 0 or 1; f ref = 800mhz; q0 to q3 terminated 100 ? between nqx, qx 84 100 ma sel = 0 or 1; f ref = 2ghz; q0 to q3 terminated 100 ? between nqx, qx 84 100 ma symbol parameter test conditio ns minimum typical maximum units v di3 open-pin voltage (default state) sel open v dd / 2 v v ih input high voltage sel 0.7 * v dd v dd + 0.3 v v il input low voltage sel -0.3 0.2 * v dd v i ih input high current sel v dd = v in = 2.625v 150 a i il input low current sel v dd = 2.625v, v in = 0v -150 a
IDT8SLVD1204I data sheet 2:4, lvds output fanout buffer, 2.5v 4 revision a 07/10/14 table 4c. differential input dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input volta ge is defined at the crosspoint. table 4d. lvds dc characteristics, v dd = 2.5v 5%, t a = -40c to 85 symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk0, npclk1 pclk1, npclk1 v dd = v in = 2.625v 150 a i il input low current pclk0, pclk1 v dd = 2.625v, v in = 0v -10 a npclk0, npclk1 v dd = 2.625v, v in = 0v -150 a v ref reference voltage for input bias i ref = 1ma v dd ? 1.50 v dd ? 1.35 v dd ? 1.15 v v pp peak-to-peak voltage; note 1 f ref < 1.5 ghz 0.1 1.5 v f ref > 1.5 ghz 0.2 1.5 v v cmr common mode input voltage; note 1, 2 1.0 v dd ? 0.6 v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 250 450 mv ? v od v od magnitude change 50 mv v os offset voltage 1.15 1.45 v ? v os v os magnitude change 50 mv
IDT8SLVD1204I data sheet revision a 07/10/14 5 2:4, lvds output fanout buffer, 2.5v ac electrical characteristics table 5. ac electrical characteristics, v dd = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the differential input cr osspoint to the different ial output crosspoint. note 2: defined as skew between outputs at the same supply voltage and with equal lo ad conditions. measured at the differential crosspoint. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs on different devices o perating at the same supply voltage, same frequency, same tempera ture and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential crosspoi nt. note 5: qx, nqx outputs measured differentially. see mux isolation diagram in the parameter measurement information section. symbol parameter test conditio ns minimum typical maximum units f ref input frequency pclk[0:1], npclk[0:1] 2ghz ? v/ ? t input edge rate pclk[0:1], npclk[0:1] 1.5 v/ns t pd propagation delay; note 1 pclk[0:1], npclk[0:1] to any qx, nqx for v pp = 0.1v or 0.3v 120 210 300 ps t sk(o) output skew; note 2, 3 20 ps t sk(i) input skew; note 3 20 ps t sk(p) pulse skew f ref = 100mhz 15 ps t sk(pp) part-to-part skew; note 3, 4 230 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section f ref = 122.88mhz square wave, v pp = 1v, integration range: 1khz ? 40mhz 138 205 fs f ref = 122.88mhz square wave, v pp = 1v, integration range: 10khz ? 20mhz 92 135 fs f ref = 122.88mhz square wave, v pp = 1v, integration range: 12khz ? 20mhz 92 135 fs f ref = 156.25mhz square wave, v pp = 1v, integration range: 1khz ? 40mhz 89 130 fs f ref = 156.25mhz square wave, v pp = 1v, integration range: 10khz ? 20mhz 65 95 fs f ref = 156.25mhz square wave, v pp = 1v, integration range: 12khz ? 20mhz 65 95 fs f ref = 156.25mhz square wave, v pp = 0.5v, integration range: 1khz ? 40mhz 87 130 fs f ref = 156.25mhz square wave, v pp = 0.5v, integration range: 10khz ? 20mhz 64 95 fs f ref = 156.25mhz square wave, v pp = 0.5v, integration range: 12khz ? 20mhz 64 95 fs t r / t f output rise/ fall time 20% to 80% outputs loaded with 100 ? 40 250 ps mux isolation mux isolation; note 5 f ref = 100mhz 72 db
IDT8SLVD1204I data sheet 2:4, lvds output fanout buffer, 2.5v 6 revision a 07/10/14 additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundament al frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications , phase noise measurements have issues relating to the limitations of the measurement equipment. the noise floor of the equipment can be higher or lower than the noise floor of the device. additive phase noise is dependent on both the noise floor of the input source and measurement equipment. measured using a wenzel 156.25mhz oscillator as the input source. additive phase jitter @ 156.25mhz, v pp = 1v, integration range (12khz to 20mhz) = 65fs (typical) ssb phase noise (dbc/hz) offset from carr ier frequency (hz)
IDT8SLVD1204I data sheet revision a 07/10/14 7 2:4, lvds output fanout buffer, 2.5v parameter measureme nt information lvds output load test circuit pulse skew part-to-part skew differential input level output skew output rise/fall time v dd t plh t phl tsk(p) = |t phl - t plh | pclk[0:1] npclk[0:1] qy nqy t sk(pp) part 1 part 2 qx nqx qy nqy v dd gnd npclk[0:1] pclk[0:1] qx nqx qy nqy nq[0:3] q[0:3] 20% 80% 80% 20% t r t f v od
IDT8SLVD1204I data sheet 2:4, lvds output fanout buffer, 2.5v 8 revision a 07/10/14 parameter measurement in formation, continued input skew propagation delay differential output voltage setup mux isolation offset voltage setup t pd2 t pd1 tsk(i) = |t pd1 - t pd2 | tsk(i) npclk1 pclk1 nq[0:3] q[0:3] npclk0 pclk0 t pd nq[0:3] q[0:3] npclk[0:1] pclk[0:1] amplitude (db) a0 spectrum of output signal q mux _isolation = a0 ? a1 (fundamental) frequency ? mux selects other input mux selects active input clock signal a1
IDT8SLVD1204I data sheet revision a 07/10/14 9 2:4, lvds output fanout buffer, 2.5v applications information recommendations for unused input and output pins inputs: pclk/npclk inputs for applications not requiring the use of a differential input, both the pclk and npclk pins can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from pclk to ground. outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v1 = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 2.5v, r1 and r2 value should be adjusted to set v1 at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requir es that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels
IDT8SLVD1204I data sheet 2:4, lvds output fanout buffer, 2.5v 10 revision a 07/10/14 2.5v lvpecl clock input interface the pclk /npclk accepts lvpecl, lvds, and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2c show interface examples for the pclk/ npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2a. pclk/npclk input driven by a 2.5v lvpecl driver figure 2c. pclk/npclk input driven by a 2.5v lvds driver figure 2b. pclk/npclk input driven by a 2.5v lvpecl driver with ac couple 2. 5v p c l k np c l k 2. 5v 2. 5v lvpe cl lvpe c l in p u t p c l k np c l k
IDT8SLVD1204I data sheet revision a 07/10/14 11 2:4, lvds output fanout buffer, 2.5v lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output struct ures: current source and voltage source. the standard termination schematic as shown in figure 3a can be used with either type of output structure. figure 3b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter comm on mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the out put structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lvds termination lv d s driver lv d s driver lv d s receiver lv d s receiver z t c z o ? z t z o ? z t z t 2 z t 2 figure 3a. standard termination figure 3b. optional termination
IDT8SLVD1204I data sheet 2:4, lvds output fanout buffer, 2.5v 12 revision a 07/10/14 vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 4. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
IDT8SLVD1204I data sheet revision a 07/10/14 13 2:4, lvds output fanout buffer, 2.5v power considerations this section provides information on power dissipation and junc tion temperature for the IDT8SLVD1204I. equations and example ca lculations are also provided. 1. power dissipation. the total power dissipation for the IDT8SLVD1204I is the sum of the core power plus the output power dissipation due to the loa d. the following is the power dissipation for v dd = 2.5v + 5% = 2.625v, which gives worst case results. ? total power (core)max = v dd_max * i dd_max = 2.625v * 100ma = 262.5mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the app ropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 74.7c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.263w * 74.7c/w = 104.6c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 16-lead vfqfn, forced convection ? ja at 0 air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 74.7c/w 65.3c/w 58.5c/w
IDT8SLVD1204I data sheet 2:4, lvds output fanout buffer, 2.5v 14 revision a 07/10/14 reliability information table 7. ? ja vs. air flow table for a 16-lead vfqfn transistor count the transistor count for the IDT8SLVD1204I is: 417 ? ja at 0 air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 74.7c/w 65.3c/w 58.5c/w
IDT8SLVD1204I data sheet revision a 07/10/14 15 2:4, lvds output fanout buffer, 2.5v 16-lead vfqfn package out line and package dimensions
IDT8SLVD1204I data sheet 2:4, lvds output fanout buffer, 2.5v 16 revision a 07/10/14 ordering information table 8. ordering information table 9. pin 1 orientation in tape and reel packaging part/order number marking package shipping packaging temperature 8slvd1204nlgi 1204i ?lead-free? 16-lead vfqfn tube -40 ? c to 85 ? c 8slvd1204nlgi8 1204i ?lead-free? 16-lead vfqfn tape & reel, pin 1 orientation: eia-481-c -40 ? c to 85 ? c 8slvd1204nlgi/w 1204i ?lead-free? 16-lead vfqfn tape & reel, pin 1 orientation: eia-481-d -40 ? c to 85 ? c part number suffix pin 1 orientation illustration 8 quadrant 1 (eia-481-c) /w quadrant 2 (eia-481-d) u s er direction of feed correct pin 1 orientation carrier tape top s ide (ro u nd s procket hole s ) u s er direction of feed correct pin 1 orientation carrier tape top s ide (ro u nd s procket hole s )
IDT8SLVD1204I data sheet revision a 07/10/14 17 2:4, lvds output fanout buffer, 2.5v revision history sheet rev table page description of change date a t8 16 ordering info: changed tray to tube. 2/26/2014 a 1 corrected part number 7/8/2014
disclaimer integrated device technology, inc. (idt) and its subs idiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any li cense under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this produ ct is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recomme nded without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices o r critical medical instruments. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2014 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support email: clocks@idt.com

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